Processors and related computer components are becoming more powerful with increasing capabilities, resulting in increasing amounts of heat dissipated from these components. Similarly, package and die sizes of the components are decreasing or remaining the same, which increases the amount of heat energy given off by the component for a given unit of surface area. Furthermore, as computer-related equipment becomes more powerful, more chips are mounted to the printed circuit board, and more and more components are being placed inside the equipment or chassis which is also decreasing in size, resulting in additional heat generation in a smaller volume of space. Increased temperatures can potentially damage the components of the equipment, or reduce the lifetime of the individual components and equipment. In addition, some components, such as ILD layers in microelectronic dies, are more susceptible to damage resulting from stress and strain occurring during testing, packaging, and use.
For example, part of a process flow for packaging a microelectronic die may include flip chip attach processes, which typically involve a reflow of solder bumps to form solder joints between a die and substrate. Usually, temperatures necessary to reflow the solder bumps lead to an expansion of each of the die and the substrate. During cooling, different shrinkage amounts of the die and substrate could lead to cracks within the die, especially when a mechanically weak interlayer dielectric (ILD) is used on the die. The ILD of the die usually tends to experience increased thermo-mechanical stresses in the area under the solder joints during die and substrate attach, which stresses lead to increased under bump ILD cracking. Because of the above disadvantages with effecting a direct joining of die and substrate, as mentioned above, underfill materials are sometimes used to redistribute the stress generated due to the CTE mismatch across the whole package. However, disadvantageously, in view of a trend toward using ultra low-k inter layer dielectrics (ILD's) as part of microelectronic dies, sometimes even the use of underfill materials cannot compensate for the resultant increased fragility of the die in the face of CTE mismatches during testing, packaging and use.
Another part of a process flow for packaging a microelectronic die may bonding a microelectronic die to a heat spreader, which may involve a packaging technology that places one or more thinned dice on a planar heat spreader and secures the dice on to the heat spreader using a bonding process involving an adhesive material, such as solder, or a polymeric material, or, in the alternative, using a direct metallurgical bond, such as may be formed by an interdiffusion of Au (gold) and Si (silicon). Where a metallurgical bond is to be established as noted above, such a prior art process however requires a heating of the die/heat spreader assembly in order to form the bond. Disadvantageously, however, heating to create the bond as noted above may involve temperatures from about 150 to about 300 degrees Celsius, and may as a result, similar to the flip chip process, create unwanted stresses and cracking involving the die, the heat spreader and/or the bonding material (or thermal interface material, hereinafter “TIM”) therebetween during a cool down phase of the bonding process. Unwanted stresses on the die can disadvantageously have a negative impact on the performance of circuit components on the die.
In order to overcome the above disadvantages, the prior art has proposed the use of thin die thin thermal interface material (TIM) typically involving the use of dies having a thickness of about 100 microns or less. The use of cooling micro-channels have also been explored by the prior art as a potential thermal solution for future microelectronic packages. Thin die thin thermal interface material (TDTT) dies, however, typically use relatively large heat spreaders that make the handling of the package during a mounting of the die onto the substrate difficult. Moreover, micro-channels are typically expensive to produce, requiring extra components such as pumps and pipes, ad thus further introducing added reliability issues with respect to package cooling. In addition, the use of ceramic or other lower CTE substrates have been proposed to address the results of a CTE mismatch between the substrate and a die. However, such substrates are more expensive and have a higher dielectric constant than typical substrates, and can thus have a negative effect on the performance of the package as a whole.
The prior art fails to provide a reliable, simple and cost-effective technique of providing a microelectronic die exhibiting improved heat dissipation characteristics.
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